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TCAD
1998
119views more  TCAD 1998»
13 years 7 months ago
A controller redesign technique to enhance testability of controller-data path circuits
—We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have ...
Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
DSD
2007
IEEE
98views Hardware» more  DSD 2007»
14 years 1 months ago
Fault Diagnosis in Integrated Circuits with BIST
This paper presents an optimized fault diagnosing procedure applicable in Built-in Self-Test environments. Instead of the known approach based on a simple bisection of patterns in...
Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evart...
ITC
1998
IEEE
73views Hardware» more  ITC 1998»
13 years 11 months ago
Maximization of power dissipation under random excitation for burn-in testing
This work proposes an approach to generate weighted random patterns which can maximally excite a circuit during its burn-in testing. The approach is based on a probability model a...
Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen
ICCAD
1994
IEEE
110views Hardware» more  ICCAD 1994»
13 years 11 months ago
Test pattern generation based on arithmetic operations
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
ICIP
2006
IEEE
14 years 9 months ago
Hardware Computation of Moment Functions in a Silicon Retina using Binary Patterns
We present in this paper a method for implementing moment functions in a CMOS retina for shape recognition applications. The method is based on the use of binary patterns and it a...
Olivier Aubreton, Lew Fock Chong Lew Yan Voon, Guy...