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ISCAS
2006
IEEE
150views Hardware» more  ISCAS 2006»
14 years 1 months ago
A character size optimization technique for throughput enhancement of character projection lithography
— We propose a character size optimization technique to enhance the throughput of maskless lithography as well as photomask manufacture. The number of electron beam shots to draw...
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryo...
AUTOID
2005
IEEE
14 years 1 months ago
Impedance Matching Concepts in RFID Transponder Design
In this paper, we analyze impedance matching concepts in passive radio frequency identification (RFID) transponders, which are powered by the incoming RF energy and consist of an...
K. V. S. Rao, Pavel V. Nikitin, Sander F. Lam
VTS
2005
IEEE
96views Hardware» more  VTS 2005»
14 years 1 months ago
Implementing a Scheme for External Deterministic Self-Test
A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an ...
Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valent...
DAC
2000
ACM
13 years 12 months ago
Modeling and simulation of real defects using fuzzy logic
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
Amir Attarha, Mehrdad Nourani, Caro Lucas
VTS
1996
IEEE
76views Hardware» more  VTS 1996»
13 years 11 months ago
Test point insertion based on path tracing
This paper presents an innovative method for inserting test points in the circuit-under-test to obtain complete fault coverage for a specified set of test patterns. Rather than us...
Nur A. Touba, Edward J. McCluskey