376 search results - page 59 / 76 » Self-Assembled Circuit Patterns |
ET
2010
13 years 6 months ago
2010
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
CHI
2007
ACM
14 years 8 months ago
2007
ACM
In this paper, we introduce the versatile creative tool called "I/O Plant" which generates new-style interactions among humans, plants and computers. It enables designer...
DCC
2008
IEEE
14 years 7 months ago
2008
IEEE
We introduce an EDIF netlist graph algorithm which is lossy with respect to the original byte stream but lossless in terms of the circuit information it contains based on a graph ...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steadystate thermal analysis. This paper presents the first ...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...