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DAC
2008
ACM
14 years 8 months ago
Scan chain clustering for test power reduction
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2007
ACM
14 years 8 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2000
ACM
14 years 8 months ago
Self-test methodology for at-speed test of crosstalk in chip interconnects
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
Xiaoliang Bai, Sujit Dey, Janusz Rajski
DAC
2003
ACM
14 years 8 months ago
Seed encoding with LFSRs and cellular automata
Reseeding is used to improve fault coverage of pseudorandom testing. The seed corresponds to the initial state of the PRPG before filling the scan chain. In this paper, we present...
Ahmad A. Al-Yamani, Edward J. McCluskey
DAC
2004
ACM
14 years 8 months ago
Profile-guided microarchitectural floorplanning for deep submicron processor design
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watew...