605 search results - page 110 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
HPCA
2002
IEEE
14 years 7 months ago
2002
IEEE
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
ISPAN
2008
IEEE
14 years 1 months ago
2008
IEEE
- Many peer-to-peer file sharing systems have been proposed to take the locality and heterogeneity into account. The two-layered architecture is one of the most widespread systems ...
BMCBI
2008
13 years 7 months ago
2008
Background: Testing for selection is becoming one of the most important steps in the analysis of multilocus population genetics data sets. Existing applications are difficult to u...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
We present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic-structures and both die-to-die and with...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is be...