605 search results - page 20 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch--an approach to improving single-threaded application performance by using help...
RTSS
2006
IEEE
14 years 1 months ago
2006
IEEE
Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— In this paper, we present a comprehensive energy estimation framework for software executing on Very Long Instruction Word (VLIW) processor cores. The proposed energy model is ...