605 search results - page 27 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
ITNG
2010
IEEE
13 years 5 months ago
2010
IEEE
—The increase in computational power of off-the-shelf hardware offers more and more advantageous tradeoffs among efficiency, cost and availability, thus enhancing the feasibil...
HPCA
2008
IEEE
14 years 1 months ago
2008
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
ICS
2004
Tsinghua U.
14 years 23 days ago
2004
Tsinghua U.
Studying program behavior is a central component in architectural designs. In this paper, we study and exploit one aspect of program behavior, the behavior repetition, to expedite...
HIPEAC
2007
Springer
13 years 11 months ago
2007
Springer
In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-den...
ICIP
1999
IEEE
14 years 9 months ago
1999
IEEE
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...