605 search results - page 34 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
MICRO
1998
IEEE
14 years 23 days ago
1998
IEEE
Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geomet...
HPDC
2010
IEEE
13 years 9 months ago
2010
IEEE
MapReduce programming model has simplified the implementation of many data parallel applications. The simplicity of the programming model and the quality of services provided by m...
DAC
1998
ACM
14 years 9 months ago
1998
ACM
Memory is one of the most restricted resources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressed code CPU, a cach...
CMG
2000
13 years 10 months ago
2000
Our study compares CPU performance on RISC and CISC uni and multiprocessors of varying speeds, and shows that the Instruction Set Architecture (ISA) style no longer matters. Our s...