605 search results - page 7 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
An experimental set of tools that generate instruction set simulators, assemblers, and disassemblers from a single description was developed to test if retargetable development to...
MSE
2003
IEEE
14 years 18 days ago
2003
IEEE
Computer architecture is often taught by having students use software to design and simulate individual pieces of a computer processor. We have developed a method that will take t...
DAC
1992
ACM
13 years 11 months ago
1992
ACM
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
Presentation
Data-parallel architectures like SIMD (Single Instruction Multiple Data) or SIMT (Single Instruction Multiple Thread) have been adopted in many recent CPU and GPU architectures. Al...