605 search results - page 8 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Composable multicore systems merge multiple independent cores for running sequential single-threaded workloads. The performance scalability of these systems, however, is limited d...
APCSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
DAC
2004
ACM
14 years 23 days ago
2004
ACM
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a p...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...