605 search results - page 91 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
DAC
2003
ACM
14 years 9 months ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
EUROPAR
1997
Springer
14 years 19 days ago
1997
Springer
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
SIGGRAPH
1991
ACM
13 years 12 months ago
1991
ACM
The number of polygons comprising interesting architectural models is many more than can be rendered at interactive frame rates. However, due to occlusion by opaque surfaces (e.g....
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper we explore a new clustering approach for reducing the complexity of wide issue in-order processors based on EPIC architectures. Complexity effectiveness is achieved ...