605 search results - page 9 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compi...
SAMOS
2010
Springer
13 years 5 months ago
2010
Springer
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
CAMP
2005
IEEE
14 years 29 days ago
2005
IEEE
— This paper describes the mapping of a recently introduced template matching algorithm based on the Normalized Cross Correlation (NCC) on a general purpose processor endowed wit...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...