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DATE
1998
IEEE
76views Hardware» more  DATE 1998»
13 years 11 months ago
Gated Clock Routing Minimizing the Switched Capacitance
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
Jaewon Oh, Massoud Pedram
ASPDAC
2009
ACM
184views Hardware» more  ASPDAC 2009»
13 years 11 months ago
FastRoute 4.0: global router with efficient via minimization
The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by chargin...
Yue Xu, Yanheng Zhang, Chris Chu
INFOCOM
1997
IEEE
13 years 11 months ago
Performance Modelling of Reliable Multicast Transmission
Our aim is to investigate reliable transmission for multicast communication and explore its relationship to multicast routing. We derive two characterizations that enable the comp...
Jörg Nonnenmacher, Ernst Biersack
INFOCOM
2000
IEEE
13 years 11 months ago
Near Optimal Routing Lookups with Bounded Worst Case Performance
Abstract—The problem of route address lookup has received much attention recently and several algorithms and data structures for performing address lookups at high speeds have be...
Pankaj Gupta, Balaji Prabhakar, Stephen P. Boyd
ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Skew scheduling and clock routing for improved tolerance to process variations
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu