This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by chargin...
Our aim is to investigate reliable transmission for multicast communication and explore its relationship to multicast routing. We derive two characterizations that enable the comp...
Abstract—The problem of route address lookup has received much attention recently and several algorithms and data structures for performing address lookups at high speeds have be...
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...