625 search results - page 90 / 125 » Semi-preemptive routing on trees |
ISPD
1999
ACM
14 years 24 days ago
1999
ACM
Buffer insertion is an effective approach to achieve both minimal clock signal delay and skew in high speed VLSI circuit design. In this paper, we develop an optimal buffer ins...
COMCOM
2008
13 years 8 months ago
2008
Overlay routing has been proposed to enhance the reliability and performance of IP networks, since it can bypass congestion and transient outages by forwarding traffic through one ...
QUESTA
2008
13 years 8 months ago
2008
We consider a discrete-time tree network of polling servers where all packets are routed to the same node (called node 0), from which they leave the network. All packets have unit...
ICCAD
2010
IEEE
13 years 6 months ago
2010
IEEE
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
HPSR
2011
12 years 8 months ago
2011
Abstract—This paper describes the implementation of ARPPath (a.k.a. FastPath) bridges, a recently proposed concept for low latency bridges, in Linux/Soekris and OpenFlow/NetFPGA ...