Buffer insertion is an effective approach to achieve both minimal clock signal delay and skew in high speed VLSI circuit design. In this paper, we develop an optimal buffer ins...
Overlay routing has been proposed to enhance the reliability and performance of IP networks, since it can bypass congestion and transient outages by forwarding traffic through one ...
We consider a discrete-time tree network of polling servers where all packets are routed to the same node (called node 0), from which they leave the network. All packets have unit...
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, ...
Abstract—This paper describes the implementation of ARPPath (a.k.a. FastPath) bridges, a recently proposed concept for low latency bridges, in Linux/Soekris and OpenFlow/NetFPGA ...