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» Sensitivity analysis in decision circuits
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LCPC
2007
Springer
14 years 3 months ago
Using ZBDDs in Points-to Analysis
Binary Decision Diagrams (BDDs) have recently become widely accepted as a space-efficient method of representing relations in points-to analyses. When BDDs are used to represent re...
Ondrej Lhoták, Stephen Curial, José ...
ASYNC
2002
IEEE
124views Hardware» more  ASYNC 2002»
14 years 2 months ago
Synchronous Interlocked Pipelines
In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease...
Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Pe...
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
14 years 9 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
GLVLSI
2006
IEEE
143views VLSI» more  GLVLSI 2006»
14 years 3 months ago
SACI: statistical static timing analysis of coupled interconnects
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, A...
DAC
2006
ACM
14 years 10 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...