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» Sensitivity analysis in decision circuits
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EURODAC
1994
IEEE
141views VHDL» more  EURODAC 1994»
14 years 1 months ago
Exact path sensitization in timing analysis
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...
R. Peset Llopis
ISBI
2008
IEEE
14 years 9 months ago
Increased sensitivity in FMRI group analysis using mixed-effect modeling
In functional Magnetic Resonance Imaging group studies, uncertainties on the individual BOLD responses are not taken into account by standard detection procedures, which may limit...
Merlin Keller, Alexis Roche
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
14 years 6 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
14 years 1 months ago
On Applying Incremental Satisfiability to Delay Fault Testing
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah...
EOR
2006
66views more  EOR 2006»
13 years 9 months ago
Using intervals for global sensitivity and worst-case analyses in multiattribute value trees
Sensitivity analyses have long been used to assess the impacts of uncertainties on outcomes of decision models. Several approaches have been suggested, but it has been problematic...
Jyri Mustajoki, Raimo P. Hämäläinen...