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» Sequential Circuits for Relational Analysis
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ICCAD
2001
IEEE
124views Hardware» more  ICCAD 2001»
14 years 6 months ago
Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs
Methods based on Boolean satisfiability (SAT) typically use a Conjunctive Normal Form (CNF) representation of the Boolean formula, and exploit the structure of the given problem ...
Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zh...
FMCAD
2004
Springer
14 years 2 months ago
Increasing the Robustness of Bounded Model Checking by Computing Lower Bounds on the Reachable States
Most symbolic model checkers are based on either Binary Decision Diagrams (BDDs), which may grow exponentially large, or Satisfiability (SAT) solvers, whose time requirements rapi...
Mohammad Awedh, Fabio Somenzi
SCP
2010
126views more  SCP 2010»
13 years 7 months ago
Component simulation-based substitutivity managing QoS and composition issues
Several scientic bottlenecks have been identied in existing component-based approaches. em, we focus on the identication of a relevant abstraction for the component expression ...
Pierre-Cyrille Héam, Olga Kouchnarenko, J&e...
DAC
2005
ACM
14 years 10 months ago
A non-parametric approach for dynamic range estimation of nonlinear systems
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
Bin Wu, Jianwen Zhu, Farid N. Najm
DAC
2010
ACM
14 years 1 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...