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» Sequential Circuits for Relational Analysis
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ISLPED
1997
ACM
83views Hardware» more  ISLPED 1997»
13 years 11 months ago
A symbolic algorithm for low-power sequential synthesis
We present an algorithm that restructures the state transition graph STG of a sequential circuit so as to reduce power dissipation. The STG is modi ed without changing the behav...
Balakrishna Kumthekar, In-Ho Moon, Fabio Somenzi
ATS
1998
IEEE
76views Hardware» more  ATS 1998»
13 years 11 months ago
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits
We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: 1 fault-list and te...
Michael S. Hsiao, Srimat T. Chakradhar
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
13 years 10 months ago
Efficient incremental clock latency scheduling for large circuits
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
Christoph Albrecht
ICCAD
2006
IEEE
183views Hardware» more  ICCAD 2006»
14 years 4 months ago
Soft error derating computation in sequential circuits
Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), ...
Hossein Asadi, Mehdi Baradaran Tahoori
UAI
2008
13 years 8 months ago
Sensitivity analysis in decision circuits
Decision circuits have been developed to perform efficient evaluation of influence diagrams [Bhattacharjya and Shachter, 2007], building on the advances in arithmetic circuits for...
Debarun Bhattacharjya, Ross D. Shachter