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» Sequential circuits for program analysis
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ISQED
2006
IEEE
147views Hardware» more  ISQED 2006»
14 years 1 months ago
Compact Reduced Order Modeling for Multiple-Port Interconnects
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng ...
JPDC
2011
137views more  JPDC 2011»
12 years 10 months ago
Transparent runtime parallelization of the R scripting language
Scripting languages such as R and Matlab are widely used in scientific data processing. As the data volume and the complexity of analysis tasks both grow, sequential data process...
Jiangtian Li, Xiaosong Ma, Srikanth B. Yoginath, G...
ISQED
2010
IEEE
177views Hardware» more  ISQED 2010»
14 years 2 months ago
Multi-corner, energy-delay optimized, NBTI-aware flip-flop design
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
Hamed Abrishami, Safar Hatami, Massoud Pedram
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 17 days ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
COMPSAC
2005
IEEE
14 years 1 months ago
Parallel Changes: Detecting Semantic Interferences
Parallel changes are a basic fact of modern software development. Where previously we looked at prima facie interference, here we investigate a less direct form that we call seman...
G. Lorenzo Thione, Dewayne E. Perry