111 search results - page 3 / 23 » Serialized parallel code generation framework for MPSoC |
IPPS
1999
IEEE
13 years 12 months ago
1999
IEEE
If parallelism can be successfully exploited in a program, significant reductions in execution time can be achieved. However, if sections of the code are dominated by parallel ove...
ETT
2000
13 years 7 months ago
2000
The input-output weight enumeration (distribution) function of the ensemble of serially concatenated turbo codes is derived, where the ensemble is generated by a uniform choice ov...
DATE
2010
IEEE
14 years 19 days ago
2010
IEEE
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...
TIT
2008
13 years 7 months ago
2008
Abstract--Low-Density Parity-Check (LDPC) codes are usually decoded by running an iterative belief-propagation algorithm over the factor graph of the code. In the traditional messa...