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ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
14 years 4 months ago
A low power merge cell processor for real-time spike sorting in implantable neural prostheses
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
M. D. Linderman, T. H. Meng
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
14 years 4 months ago
Analysis and optimization of gate leakage current of power gating circuits
— Power gating is widely accepted as an efficient way to suppress subthreshold leakage current. Yet, it suffers from gate leakage current, which grows very fast with scaling dow...
Hyung-Ock Kim, Youngsoo Shin
VLSID
2003
IEEE
115views VLSI» more  VLSID 2003»
14 years 11 months ago
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
W. Kuang, J. S. Yuan
ICRA
2009
IEEE
147views Robotics» more  ICRA 2009»
14 years 5 months ago
Milligram-scale high-voltage power electronics for piezoelectric microrobots
— Piezoelectric actuators can achieve high efficiency and power density in very small geometries, which shows promise for microrobotic applications, such as flapping-wing robot...
Michael Karpelson, Gu-Yeon Wei, Robert J. Wood
ICC
2008
IEEE
100views Communications» more  ICC 2008»
14 years 5 months ago
Power Scheduling for MIMO Relay Channels Employing Rateless Codes
—We propose a simple power scheduling algorithm for relay channels with multiple antennas. The algorithm combines seamlessly with a low complexity communication protocol that emp...
Youjian Liu, Mahesh K. Varanasi, Xinming Huang