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MICRO
2003
IEEE
128views Hardware» more  MICRO 2003»
15 years 7 months ago
IPStash: a Power-Efficient Memory Architecture for IP-lookup
Abstract—High-speed routers often use commodity, fully-associative, TCAMs (Ternary Content Addressable Memories) to perform packet classification and routing (IP lookup). We prop...
Stefanos Kaxiras, Georgios Keramidas
AUTOMATICA
2008
89views more  AUTOMATICA 2008»
15 years 2 months ago
Dynamic buffer management using optimal control of hybrid systems
This paper studies a general dynamic buffer management problem with one buffer inserted between two interacting components. The component to be controlled is assumed to have multi...
Wei Zhang, Jianghai Hu
AUTOMATICA
2006
113views more  AUTOMATICA 2006»
15 years 2 months ago
Least costly identification experiment for control
All approaches to optimal experiment design for control have so far focused on deriving an input signal (or input signal spectrum) that minimizes some control-oriented measure of ...
Xavier Bombois, Gérard Scorletti, Michel Ge...
IJES
2008
130views more  IJES 2008»
15 years 2 months ago
Deriving efficient control in Process Networks with Compaan/Laura
: At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map rapidly and efficiently signal processing applications written ...
Steven Derrien, Alexandru Turjan, Claudiu Zissules...
DAC
2002
ACM
16 years 3 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy