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IPPS
2006
IEEE
14 years 5 months ago
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal
Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
Yoshihiro Nakatani, Masanori Hariyama, Michitaka K...
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
14 years 4 months ago
An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...
Michalis D. Galanis, Gregory Dimitroulakos, Consta...
ASAP
1997
IEEE
93views Hardware» more  ASAP 1997»
14 years 3 months ago
A Novel Sequencer Hardware for Application Specific Computing
This paper introduces a powerful novel sequencer for controlling computational machines and for structured DMA (direct memory access) applications. It is mainly focused on applica...
Reiner W. Hartenstein, Jürgen Becker, Michael...
DATE
2003
IEEE
63views Hardware» more  DATE 2003»
14 years 4 months ago
NPSE: A High Performance Network Packet Search Engine
This paper describes the NPSE, a high-performance SRAM-based network packet search engine which has the primary application of supporting IPv4 and IPv6 forwarding. It is based on ...
Naresh Soni, Nick Richardson, Lun Bin Huang, Sures...
ASPLOS
2008
ACM
14 years 1 months ago
Archipelago: trading address space for reliability and security
Memory errors are a notorious source of security vulnerabilities that can lead to service interruptions, information leakage and unauthorized access. Because such errors are also ...
Vitaliy B. Lvin, Gene Novark, Emery D. Berger, Ben...