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IPPS
2008
IEEE
14 years 3 months ago
Automatic generation of a parallel sorting algorithm
In this paper, we discuss a library generator for parallel sorting routines that examines the input characteristics (and the parameters they affect) to select the best performing ...
Brian A. Garber, Daniel Hoeflinger, Xiaoming Li, M...
ICCD
1994
IEEE
85views Hardware» more  ICCD 1994»
14 years 1 months ago
A Superassociative Tagged Cache Coherence Directory
Dynamically tagged directories are memory-efficient mechanisms for maintaining cache coherence in sharedmemory multiprocessors. These directories use specialpurpose caches of poin...
David J. Lilja, Shanthi Ambalavanan
ECRTS
2009
IEEE
13 years 6 months ago
On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
DAC
2004
ACM
14 years 9 months ago
Multi-profile based code compression
Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio...
Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Ce...
CASES
2001
ACM
14 years 15 days ago
Computation offloading to save energy on handheld devices: a partition scheme
We consider handheld computing devices which are connected to a server (or a powerful desktop machine) via a wireless LAN. On such devices, it is often possible to save the energy...
Zhiyuan Li, Cheng Wang, Rong Xu