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DAC
2006
ACM
14 years 9 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
14 years 2 months ago
Energy reduction in multiprocessor systems using transactional memory
The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Until recently, this trend was mostly true for uniproc...
Tali Moreshet, R. Iris Bahar, Maurice Herlihy
INFOCOM
1995
IEEE
14 years 8 days ago
Measuring the Performance of Parallel Message-Based Process Architectures
Message-based process architectures are widely regarded as an effective method for structuring parallel protocol processing on shared memory multi-processor platforms. A message-b...
Douglas C. Schmidt, Tatsuya Suda
HPCA
1997
IEEE
14 years 29 days ago
Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...
Thomas Stricker, Thomas R. Gross
WSC
1997
13 years 10 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson