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MICRO
2007
IEEE
139views Hardware» more  MICRO 2007»
14 years 3 months ago
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP) system. Memory requests from different threads can interfere with each other. Existing memory acc...
Onur Mutlu, Thomas Moscibroda
ASPDAC
2001
ACM
137views Hardware» more  ASPDAC 2001»
14 years 17 days ago
Optimized address assignment for DSPs with SIMD memory accesses
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
Markus Lorenz, David Koffmann, Steven Bashford, Ra...
DSD
2010
IEEE
112views Hardware» more  DSD 2010»
13 years 7 months ago
Re-NUCA: Boosting CMP Performance Through Block Replication
— Chip Multiprocessor (CMP) systems have become the reference architecture for designing micro-processors, thanks to the improvements in semiconductor nanotechnology that have co...
Pierfrancesco Foglia, Cosimo Antonio Prete, Marco ...
CF
2009
ACM
14 years 3 months ago
A light-weight fairness mechanism for chip multiprocessor memory systems
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
Magnus Jahre, Lasse Natvig
HPCC
2005
Springer
14 years 2 months ago
Transactional Cluster Computing
A lot of sophisticated techniques and platforms have been proposed to build distributed object systems. Remote method invocation and explicit message passing on top of traditional...
Stefan Frenz, Michael Schöttner, Ralph Gö...