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ISCA
2003
IEEE
108views Hardware» more  ISCA 2003»
14 years 3 months ago
Effective ahead Pipelining of Instruction Block Address Generation
On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per c...
André Seznec, Antony Fraboulet
DATE
1999
IEEE
89views Hardware» more  DATE 1999»
14 years 2 months ago
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement
Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The p...
Radim Cmar, Luc Rijnders, Patrick Schaumont, Serge...
INFOCOM
1998
IEEE
14 years 2 months ago
TCP Behavior of a Busy Internet Server: Analysis and Improvements
The rapid growth of the World Wide Web in recent years has caused a significant shift in the composition of Internet traffic. Although past work has studied the behavior of TCP dy...
Hari Balakrishnan, Venkata N. Padmanabhan, Sriniva...
EJC
2007
13 years 9 months ago
Chords of longest circuits in locally planar graphs
It was conjectured by Thomassen ([B. Alspach, C. Godsil, Cycle in graphs, Ann. Discrete Math. 27 (1985)], p. 466) that every longest circuit of a 3-connected graph must have a cho...
Ken-ichi Kawarabayashi, Jianbing Niu, Cun-Quan Zha...
EUROMICRO
1999
IEEE
14 years 2 months ago
Processing Requirements by Software Configuration Management
Short development life cycles, the importance of timeto-market and fast changes in technology influence the requirements engineering process. Requirements are exposed to changes d...
Ivica Crnkovic, Peter J. Funk, Magnus Larsson