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» Signal Probability Based Statistical Timing Analysis
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DATE
2006
IEEE
158views Hardware» more  DATE 2006»
14 years 2 months ago
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
Jayashree Sridharan, Tom Chen
ICCAD
2001
IEEE
106views Hardware» more  ICCAD 2001»
14 years 5 months ago
System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless Channels
This paper presents a new methodology for system-level power and performance analysis of wireless multimedia systems. More precisely, we introduce an analytical approach based on ...
Radu Marculescu, Amit Nandi, Luciano Lavagno, Albe...
JCDL
2009
ACM
162views Education» more  JCDL 2009»
14 years 2 months ago
Supporting analysis of future-related information in news archives and the web
A lot of future-related information is available in news articles or Web pages. This information can however differ to large extent and may fluctuate over time. It is therefore di...
Adam Jatowt, Kensuke Kanazawa, Satoshi Oyama, Kats...
P2P
2009
IEEE
137views Communications» more  P2P 2009»
14 years 2 months ago
Analysis of Failure Correlation Impact on Peer-to-Peer Storage Systems
Abstract—Peer-to-peer storage systems aim to provide a reliable long-term storage at low cost. In such systems, peers fail continuously, hence, the necessity of self-repairing me...
Olivier Dalle, Frédéric Giroire, Jul...
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 2 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...