42 search results - page 2 / 9 » Signature Rollback - A Technique for Testing Robust Circuits |
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for powerlimited applications. For this design technique to gain widespread adoption...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
ICIP
2006
IEEE
14 years 8 months ago
2006
IEEE
The most significant bit (MSB)-plane of an image is least likely to change by the most signal processing operations. Watermarking techniques are, however, unable to exploit the MS...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...