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» Signature Rollback - A Technique for Testing Robust Circuits
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ICCAD
2009
IEEE
144views Hardware» more  ICCAD 2009»
13 years 5 months ago
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits
In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die va...
Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton
IOLTS
2006
IEEE
101views Hardware» more  IOLTS 2006»
14 years 1 months ago
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor
— Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. Howeve...
Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury,...
ACSAC
2004
IEEE
13 years 11 months ago
Static Analyzer of Vicious Executables (SAVE)
Software security assurance and malware (trojans, worms, and viruses, etc.) detection are important topics of information security. Software obfuscation, a general technique that ...
Andrew H. Sung, Jianyun Xu, Patrick Chavez, Sriniv...
IOLTS
2000
IEEE
105views Hardware» more  IOLTS 2000»
14 years 5 days ago
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
Patrick Girard, Christian Landrault, Serge Pravoss...
ET
2010
98views more  ET 2010»
13 years 6 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...