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» Silicon Validation of Evolution-Designed Circuits
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ITC
2003
IEEE
172views Hardware» more  ITC 2003»
14 years 26 days ago
First IC Validation of IEEE Std. 1149.6
–This paper provides proof of concept for the newly-approved 1149.6 standard by investigating the first silicon implementation of the test receiver. EXTEST and EXTEST_PULSE tests...
Suzette Vandivier, Mark Wahl, Jeff Rearick
ISQED
2009
IEEE
111views Hardware» more  ISQED 2009»
14 years 2 months ago
Efficient statistical analysis of read timing failures in SRAM circuits
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pilegg...
ISCAS
2003
IEEE
172views Hardware» more  ISCAS 2003»
14 years 26 days ago
Performance modeling of resonant tunneling based RAMs
Tunneling based random-access memories (TRAM’s) have recently garnered a great amount of interests among the memory designers due to their intrinsic merits such as reduced power...
Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyoungho...
DT
2000
88views more  DT 2000»
13 years 7 months ago
Postsilicon Validation Methodology for Microprocessors
f abstraction as applicable to break the problem's complexity, and innovating better techniques to address complexity of new microarchitectural features. Validation techniques...
Hemant G. Rotithor
DAC
2004
ACM
14 years 8 months ago
ORACLE: optimization with recourse of analog circuits including layout extraction
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...
Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd