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VLSID
2000
IEEE
75views VLSI» more  VLSID 2000»
14 years 1 months ago
Timing Analysis with Implicitly Specified False Paths
We consider the problem of timing analysis in the presence of known false paths. The main difficulty in adaptation of classical breadth-first search to the problem is that at each...
Eugene Goldberg, Alexander Saldanha
CACM
2010
104views more  CACM 2010»
13 years 9 months ago
Faster dimension reduction
Data represented geometrically in high-dimensional vector spaces can be found in many applications. Images and videos, are often represented by assigning a dimension for every pix...
Nir Ailon, Bernard Chazelle
DATE
2009
IEEE
131views Hardware» more  DATE 2009»
14 years 3 months ago
Communication minimization for in-network processing in body sensor networks: A buffer assignment technique
—Body sensor networks are emerging as a promising platform for healthcare monitoring. These systems are composed of battery-operated embedded devices which process physiological ...
Hassan Ghasemzadeh, Nisha Jain, Marco Sgroi, Roozb...
MOBICOM
1999
ACM
14 years 1 months ago
Query Localization Techniques for On-Demand Routing Protocols in ad hoc Networks
Mobile ad hoc networks are characterized by multi-hop wireless links, absence of any cellular infrastructure, and frequent host mobility. Design of efficient routing protocols in ...
Robert Castañeda, Samir Ranjan Das
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 8 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...