109 search results - page 5 / 22 » Simplifying Instruction Issue Logic in Superscalar Processor... |
MICRO
2002
IEEE
14 years 12 days ago
2002
IEEE
In a 64-bit processor, many of the data values actually used in computations require much narrower data-widths. In this study, we demonstrate that instruction data-widths exhibit ...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
ISCAPDCS
2001
13 years 8 months ago
2001
The implementation of modern high performance computer is increasingly directed toward parallelism in the hardware. However, most of the current fetch units are limited to one bra...
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
HPCA
1999
IEEE
13 years 11 months ago
1999
IEEE
Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors. However, its performance potential under p...