109 search results - page 6 / 22 » Simplifying Instruction Issue Logic in Superscalar Processor... |
ISSS
1998
IEEE
13 years 11 months ago
1998
IEEE
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
Burch and Dill [3] described an automatic method for verifying a pipelined processor against its instruction setarchitecture(ISA). We describethree techniquesfor improving this me...
ARCS
2010
Springer
14 years 2 months ago
2010
Springer
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-ti...
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
In this paper we investigate the behavior of data prefetching on an access decoupled machine and a superscalar machine. We assess if there are bene ts to using the decoupling para...
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geomet...