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ICC
2007
IEEE
145views Communications» more  ICC 2007»
14 years 2 months ago
Lowering Error Floor of LDPC Codes Using a Joint Row-Column Decoding Algorithm
Low-density parity-check codes using the beliefpropagation decoding algorithm tend to exhibit a high error floor in the bit error rate curves, when some problematic graphical stru...
Zhiyong He, Sébastien Roy 0002, Paul Fortie...
ISCAS
2007
IEEE
149views Hardware» more  ISCAS 2007»
14 years 2 months ago
Low-Power Circuits for Brain-Machine Interfaces
—This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson’s disease, epilepsy, prosthe...
Rahul Sarpeshkar, Woradorn Wattanapanitch, Benjami...
MDM
2007
Springer
131views Communications» more  MDM 2007»
14 years 2 months ago
Q-NiGHT: Adding QoS to Data Centric Storage in Non-Uniform Sensor Networks
Storage of sensed data in wireless sensor networks is essential when the sink node is unavailable due to failure and/or disconnections, but it can also provide efficient access t...
Michele Albano, Stefano Chessa, Francesco Nidito, ...
ISCAS
2006
IEEE
112views Hardware» more  ISCAS 2006»
14 years 2 months ago
Fine-grain thermal profiling and sensor insertion for FPGAs
– Increasing logic densities and clock frequencies on FPGAs lead to rapid increase in power density, which translates to higher on-chip temperature. In this paper, we investigate...
Somsubhra Mondal, Rajarshi Mukherjee, Seda Ogrenci...
HOTI
2005
IEEE
14 years 2 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu