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DATE
2006
IEEE
135views Hardware» more  DATE 2006»
14 years 2 months ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
14 years 2 months ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane
FTCS
1998
91views more  FTCS 1998»
13 years 10 months ago
How Fail-Stop are Faulty Programs?
Most fault-tolerant systems are designed to stop faulty programs before they write permanent data or communicate with other processes. This property (halt-on-failure) forms the co...
Subhachandra Chandra, Peter M. Chen
ISCA
2007
IEEE
196views Hardware» more  ISCA 2007»
14 years 3 months ago
Anton, a special-purpose machine for molecular dynamics simulation
The ability to perform long, accurate molecular dynamics (MD) simulations involving proteins and other biological macromolecules could in principle provide answers to some of the ...
David E. Shaw, Martin M. Deneroff, Ron O. Dror, Je...
VLSID
2003
IEEE
77views VLSI» more  VLSID 2003»
14 years 9 months ago
A Methodology for Accurate Modeling of Energy Dissipation in Array Structures
There is an increasing need for obtaining a reasonably accurate estimate of energy dissipation in SoC designs. Array structures have a significant contribution to the total system...
Mahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri