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PATMOS
2004
Springer
14 years 27 days ago
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
ASPDAC
2008
ACM
127views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Power grid analysis benchmarks
ACT Benchmarks are an immensely useful tool in performing research since they allow for rapid and clear comparison between different approaches to solving CAD problems. Recent expe...
Sani R. Nassif
ICS
2009
Tsinghua U.
14 years 4 days ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
IPPS
2006
IEEE
14 years 1 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner
ICCAD
2003
IEEE
132views Hardware» more  ICCAD 2003»
14 years 4 months ago
A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines
We have created a stochastic impulse-response (IR) momentextraction algorithm for RC circuit networks. It employs a newly discovered Feynman Sum-over-Paths Postulate. Full paralle...
Yannick L. Le Coz, Dhivya Krishna, Dusan M. Petran...