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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 4 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
SOSP
2001
ACM
14 years 4 months ago
Resilient Overlay Networks
A Resilient Overlay Network (RON) is an architecture that allows distributed Internet applications to detect and recover from path outages and periods of degraded performance with...
David G. Andersen, Hari Balakrishnan, M. Frans Kaa...
CVPR
2010
IEEE
14 years 3 months ago
Toward Coherent Object Detection And Scene Layout Understanding
Detecting objects in complex scenes while recovering the scene layout is a critical functionality in many vision-based applications. Inspired by the work of [18], we advocate the ...
Yingze Bao, Min Sun, Silvio Savarese
SAC
2009
ACM
14 years 2 months ago
An empirical study of incorporating cost into test suite reduction and prioritization
Software developers use testing to gain and maintain confidence in the correctness of a software system. Automated reduction and prioritization techniques attempt to decrease the...
Adam M. Smith, Gregory M. Kapfhammer
SAC
2009
ACM
14 years 2 months ago
GTfold: a scalable multicore code for RNA secondary structure prediction
The prediction of the correct secondary structures of large RNAs is one of the unsolved challenges of computational molecular biology. Among the major obstacles is the fact that a...
Amrita Mathuriya, David A. Bader, Christine E. Hei...
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