- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
In this paper, the Simulated Evolution algorithm (SimE) is engineered to solve the optimization problem of multi-objective VLSI netlist bi-partitioning. The multi-objective versio...
Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji
We present simulations for ultra-thin body, fully-depleted, double-gate (DG) silicon-on-insulator (SOI) devices that can be readily optimized for both static power loss and perfor...
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of pow...