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JCSC
2002
129views more  JCSC 2002»
13 years 7 months ago
Leakage Current Reduction in VLSI Systems
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
David Blaauw, Steven M. Martin, Trevor N. Mudge, K...
GLVLSI
2006
IEEE
120views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Sensitivity evaluation of global resonant H-tree clock distribution networks
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
Jonathan Rosenfeld, Eby G. Friedman
TVLSI
2002
93views more  TVLSI 2002»
13 years 7 months ago
Simultaneous switching noise in on-chip CMOS power distribution networks
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
Kevin T. Tang, Eby G. Friedman
DAC
1998
ACM
14 years 8 months ago
Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics
In this paper we present a statistical method for estimating the maximum power consumption in VLSI circuits. The method is based on the theory of extreme order statistics applied ...
Qinru Qiu, Qing Wu, Massoud Pedram
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw