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ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
13 years 6 months ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
14 years 6 months ago
A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devi
—In this paper, we present an approach to nonlinear model reduction based on representing a nonlinear system with a piecewise-linear system and then reducing each of the pieces w...
Michal Rewienski, Jacob White
ITC
2003
IEEE
126views Hardware» more  ITC 2003»
14 years 2 months ago
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M....
PADS
1999
ACM
14 years 1 months ago
Exploiting Temporal Uncertainty in Parallel and Distributed Simulations
Most work to date in parallel and distributed discrete event simulation is based on assigning precise time stamps to events, and time stamp order event processing. An alternative ...
Richard Fujimoto
ICSE
2008
IEEE-ACM
14 years 10 months ago
Temporal dependency based checkpoint selection for dynamic verification of fixed-time constraints in grid workflow systems
In grid workflow systems, temporal correctness is critical to assure the timely completion of grid workflow execution. To monitor and control the temporal correctness, fixed-time ...
Jinjun Chen, Yun Yang