Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
—In this paper, we present an approach to nonlinear model reduction based on representing a nonlinear system with a piecewise-linear system and then reducing each of the pieces w...
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M....
Most work to date in parallel and distributed discrete event simulation is based on assigning precise time stamps to events, and time stamp order event processing. An alternative ...
In grid workflow systems, temporal correctness is critical to assure the timely completion of grid workflow execution. To monitor and control the temporal correctness, fixed-time ...