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DSD
2003
IEEE
138views Hardware» more  DSD 2003»
14 years 2 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
14 years 6 months ago
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
MSS
2005
IEEE
182views Hardware» more  MSS 2005»
14 years 2 months ago
Evaluation of Advanced TCP Stacks in the iSCSI Environment using Simulation Model
Enterprise storage demands have overwhelmed traditional storage mechanisms and have led to the development of Storage Area Networks (SANs). This has resulted in the design of SCSI...
Girish Motwani, K. Gopinath
GECCO
2005
Springer
128views Optimization» more  GECCO 2005»
14 years 2 months ago
Evolutionary computation applied to the tuning of MEMS gyroscopes
We propose a tuning method for MEMS gyroscopes based on evolutionary computation to efficiently increase the sensitivity of MEMS gyroscopes through tuning and, furthermore, to fin...
Didier Keymeulen, Wolfgang Fink, Michael I. Fergus...
ASPDAC
2009
ACM
100views Hardware» more  ASPDAC 2009»
14 years 3 months ago
Noise minimization during power-up stage for a multi-domain power network
– With the popularity of Multiple Power Domain (MPD) design, the multi-domain power network noise analysis and minimization is becoming important. This paper describes an efficie...
Wanping Zhang, Yi Zhu, Wenjian Yu, Amirali Shayan ...