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FPL
2008
Springer
207views Hardware» more  FPL 2008»
13 years 10 months ago
Bitstream compression techniques for Virtex 4 FPGAs
This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardwa...
Radu Stefan, Sorin Dan Cotofana
ASPDAC
2007
ACM
89views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Trace Compaction using SAT-based Reachability Analysis
In today's designs, when functional verification fails, engineers perform debugging using the provided error traces. Reducing the length of error traces can help the debugging...
Sean Safarpour, Andreas G. Veneris, Hratch Mangass...
ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
13 years 7 months ago
A3MAP: architecture-aware analytic mapping for networks-on-chip
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
Wooyoung Jang, David Z. Pan
DAC
2003
ACM
14 years 10 months ago
Coverage directed test generation for functional verification using bayesian networks
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
Shai Fine, Avi Ziv
ATVA
2004
Springer
138views Hardware» more  ATVA 2004»
14 years 24 days ago
Providing Automated Verification in HOL Using MDGs
While model checking suffers from the state space explosion problem, theorem proving is quite tedious and impractical for verifying complex designs. In this work, we present a veri...
Tarek Mhamdi, Sofiène Tahar