Sciweavers

943 search results - page 12 / 189
» Simulation based deadlock analysis for system level designs
Sort
View
DAC
2004
ACM
14 years 8 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
DATE
2005
IEEE
155views Hardware» more  DATE 2005»
14 years 1 months ago
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
This paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of RTOS simulation models in a System Level Design Language (SLD...
M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori ...
WSC
1998
13 years 8 months ago
Modeling at the Machine-Control Level Using Discrete Event Simulation (DES)
Simulation at the machine-control level plays an important role in designing machine controls and operational specifications. Recently, there has been a considerable amount of wor...
Raid Al-Aomar, Daniel Cook
CODES
1999
IEEE
13 years 12 months ago
An MPEG-2 decoder case study as a driver for a system level design methodology
We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology...
Pieter van der Wolf, Paul Lieverse, Mudit Goel, Da...
FMAM
2010
157views Formal Methods» more  FMAM 2010»
13 years 5 months ago
An Experience on Formal Analysis of a High-Level Graphical SOA Design
: In this paper, we present the experience gained with the participation in a case study in which a novel high-level design language (UML4SOA) was used to produce a service-oriente...
Maurice H. ter Beek, Franco Mazzanti, Aldi Sulova