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» Simulation based deadlock analysis for system level designs
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FMCAD
2007
Springer
14 years 21 days ago
Circuit Level Verification of a High-Speed Toggle
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates verifying digital circuits using contin...
Chao Yan, Mark R. Greenstreet
FGCS
2007
90views more  FGCS 2007»
13 years 8 months ago
Dual-Level Key Management for secure grid communication in dynamic and hierarchical groups
Grid computing is a newly developed technology for complex systems with large-scale resource sharing and multi-institutional collaboration. The prominent feature of grid computing...
Xukai Zou, Yuan-Shun Dai, Xiang Ran
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
14 years 2 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
DAC
2004
ACM
14 years 9 months ago
Abstraction of assembler programs for symbolic worst case execution time analysis
ion of Assembler Programs for Symbolic Worst Case Execution Time Analysis Tobias Schuele Tobias.Schuele@informatik.uni-kl.de Klaus Schneider Klaus.Schneider@informatik.uni-kl.de Re...
Klaus Schneider, Tobias Schüle
DAC
2006
ACM
14 years 9 months ago
Fast analysis of structured power grid by triangularization based structure preserving model order reduction
In this paper, a Triangularization Based Structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid. The power grid is...
Hao Yu, Yiyu Shi, Lei He