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» Simulation based deadlock analysis for system level designs
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DATE
2009
IEEE
126views Hardware» more  DATE 2009»
14 years 3 months ago
Fast and accurate protocol specific bus modeling using TLM 2.0
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
H. W. M. van Moll, Henk Corporaal, Víctor R...
MOBIHOC
2008
ACM
14 years 8 months ago
Rendezvous design algorithms for wireless sensor networks with a mobile base station
Recent research shows that significant energy saving can be achieved in wireless sensor networks with a mobile base station that collects data from sensor nodes via short-range co...
Guoliang Xing, Tian Wang, Weijia Jia, Minming Li
ICDE
2006
IEEE
149views Database» more  ICDE 2006»
14 years 10 months ago
How to Determine a Good Multi-Programming Level for External Scheduling
Scheduling/prioritization of DBMS transactions is important for many applications that rely on database backends. A convenient way to achieve scheduling is to limit the number of ...
Bianca Schroeder, Mor Harchol-Balter, Arun Iyengar...
ITC
2003
IEEE
127views Hardware» more  ITC 2003»
14 years 2 months ago
Testing of Droplet-Based Microelectrofluidic Systems
Composite microsystems that integrate mechanical and fluidic components are fast emerging as the next generation of system-on-chip designs. As these systems become widespread in s...
Fei Su, Sule Ozev, Krishnendu Chakrabarty
DAC
2002
ACM
14 years 9 months ago
IP delivery for FPGAs using Applets and JHDL
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
Michael J. Wirthlin, Brian McMurtrey