Sciweavers

943 search results - page 76 / 189
» Simulation based deadlock analysis for system level designs
Sort
View
ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
14 years 1 months ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel
TELETRAFFIC
2007
Springer
14 years 3 months ago
A Phase-Type Based Markov Chain Model for IEEE 802.16e Sleep Mode and Its Performance Analysis
Abstract. To support battery powered mobile broadband wireless access devices efficiently, IEEE 802.16e defines a sleep mode operation for conserving the power of mobile terminals...
Zhisheng Niu, Yanfeng Zhu, Vilius Benetis
IJCAI
1997
13 years 10 months ago
Task Ontology Makes It Easier To Use Authoring Tools
The main purpose of this paper is to illustrate the characteristics of ontology-based authoring tools for Computer Based Training (CBT) systems. It has two major advantages as fol...
Mitsuru Ikeda, Kazuhisa Seta, Riichiro Mizoguchi
DAC
2002
ACM
14 years 10 months ago
A universal technique for fast and flexible instruction-set architecture simulation
In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance ...
Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rain...
BMCBI
2011
13 years 15 days ago
Robust joint analysis allowing for model uncertainty in two-stage genetic association studies
Background: The cost efficient two-stage design is often used in genome-wide association studies (GWASs) in searching for genetic loci underlying the susceptibility for complex di...
Dongdong Pan, Qizhai Li, Ningning Jiang, Aiyi Liu,...