This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, G...
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watew...
This paper presents an efficient hierarchical 3D capacitance extraction algorithm -- ICCAP. Most previous capacitance extraction algorithms introduce intermediate variables to fac...
Abstract— Discrete power allocation strategies for amplifyand-forward cooperative networks are proposed based on selective relaying methods. The goal of power allocation is to ma...
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...