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JOLPE
2010
97views more  JOLPE 2010»
13 years 5 months ago
Low-Power Soft Error Hardened Latch
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft e...
Hossein Karimiyan Alidash, Vojin G. Oklobdzija
DSD
2007
IEEE
160views Hardware» more  DSD 2007»
14 years 1 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
TIM
2010
294views Education» more  TIM 2010»
13 years 2 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi