181 search results - page 30 / 37 » Simulation of High-Performance Memory Allocators |
FCCM
1998
IEEE
14 years 3 months ago
1998
IEEE
JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard pro...
PDPTA
2000
14 years 3 days ago
2000
Exploiting compile time knowledge to improve memory bandwidth can produce noticeable improvements at run-time [13, 1]. Allocating the data structure [13] to separate memories when...
LCTRTS
2005
Springer
14 years 4 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
CCGRID
2010
IEEE
13 years 11 months ago
2010
IEEE
In order to address the high performance I/O needs of HPC and enterprise applications, modern interconnection fabrics, such as InfiniBand and more recently, 10GigE, rely on network...
ISCA
2011
IEEE
13 years 2 months ago
2011
IEEE
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...